and I'm pushing the boundaries of wireless communications and AI via research, teaching, and innovation.
Designing and implementing cutting-edge algorithms for wireless communications and error correction.
Expertise in VHDL/Verilog for RTL design and MATLAB/Simulink for modeling.
Pioneering new techniques in wireless communication and error correction.
Understanding and designing complex communication systems.
MathWorks
As part of the MathWorks Training Team, I am responsible for developing and delivering training and workshops for engineering through MathWorks products. I also provide support and consultation to customers and partners.
IEEE Communications Letters
Oversaw peer review and evaluation of channel coding manuscripts, ensuring technical rigor, editorial quality, and impactful contributions to the communications research community.
Intel Corporation
Led algorithm development for reconfigurable space-based communications, driving error-correcting code design, RTL implementations, and rigorous validation workflows. Contributed wireless communication patents and coordinated cross-team efforts to deliver high-performance, power-efficient programmable solutions.
Boston University
Led the development of next-generation universal decoders, creating a modular C++ GRAND framework and pioneering in-decoder security algorithms for complex channels. Provided critical expertise in microchip optimization and pre-silicon validation, enabling ultra-low-energy hardware implementations.
Octasic Inc. - Canada
Designed and optimized 5G PHY systems from MATLAB models to embedded C/ASM DSP implementations, including co-development flows for proprietary chips. Spearheaded major enhancements to the 5G polar decoder and engaged with key PHY components such as LDPC codes, driving flexibility, speed, and efficiency in next-gen wireless solutions.
McGill University
Pioneered a C++ framework for polar code decoders, delivering bit-exact, quantized models to accelerate hardware design and testing. Architected advanced polar decoder implementations that achieved leading metrics in throughput, latency, energy efficiency, and error correction. Also contributed to education by shaping and teaching core courses in computer organization, digital systems, and logic design.
Middle East Technical University
Led the full ASIC development cycle through successful chip tapeout of advanced arithmetic design units, driving innovation in hardware solutions. Designed and delivered coursework in digital logic, electronics, computer architecture, and VLSI design, creating comprehensive and engaging learning experiences for students.
Intel Labs - Hillsboro, OR, USA
Developed energy-aware policies on Nehalem architecture to optimize CPU and memory efficiency, and conducted performance analysis of next-generation Intel server and PC architectures using SPEC CPU benchmarks.
Middle East Technical University
Graduated 1st in Electrical Engineering with Dean's Honor List distinction, specializing in computer architecture, digital systems, and ASIC design.
IEEE Communications Letters
Associate Editor overseeing peer review and evaluation of channel coding manuscripts, ensuring technical rigor and editorial quality.
IEEE Conferences
Technical Program Committee member for major IEEE conferences including ICC, Globecom, and WCNC.
Universities & Industry
Led courses in computer organization, digital systems, and logic design. Mentored 20+ graduate students and interns.
International Partners
Collaborated with researchers from MIT, Stanford, and leading European institutions on cutting-edge wireless technologies.
Top Journals
Regular reviewer for IEEE Transactions on Communications, IEEE Communications Letters, and other prestigious journals.
Intel Corporation
Contributed to multiple wireless communication patents and intellectual property development in space-based communications.