Hello, I'm Furkan Ercan,
and these are what I've been up to.
Lead Algorithm Development for reconfigurable space-based communications.
Error-Correcting Code Design for enhanced communication standards.
RTL Design Expertise in VHDL/Verilog for RTL design and MATLAB/Simulink for modeling.
Validation Checks and Coordination for holistic development.
Wireless Communication Patents in advanced wireless communication techniques.
Manuscript Review: Assessing channel coding manuscripts for IEEE Communications Letters, ensuring technical precision and editorial compliance.
Peer Review Coordination: Managing the peer review process, selecting reviewers, and providing feedback to enhance the quality of published content in channel coding.
Lead Algorithm Development for reconfigurable space-based communications.
Error-Correcting Code Design for enhanced communication standards.
RTL Design Expertise in VHDL/Verilog for RTL design and MATLAB/Simulink for modeling.
Validation Checks and Coordination for holistic development.
Wireless Communication Patents in advanced wireless communication techniques.
Algorithm Leadership: Led the creation of advanced algorithms, software, and hardware for next-gen universal decoding.
GRAND Framework Engineering: Engineered a dynamic C++ framework for the GRAND algorithm family, enabling versatile configurations. Served as a foundation for design, analysis, testing, and optimization.
Innovative Security Algorithms: Pioneered software-based security algorithms for complex channel conditions, using novel in-decoder methods.
Microchip Optimization Expertise: Provided expertise in optimizing resources and conducting pre-silicon validation for ultra low-energy universal decoder microchips.
5G PHY Systems Design: Led design and optimization of 5G PHY Wireless Protocol Systems, from MATLAB models to embedded C/ASM DSP implementations.
MATLAB/C Co-Development: Executed MATLAB/C co-development for proprietary wireless chips, enhancing seamless development and testbenching.
Optimization Leadership: Spearheaded optimization of the 5G polar decoder, implementing enhancements for increased flexibility and speed.
Expertise in 5G PHY Components: Engaged with critical 5G PHY components and LDPC codes.
Proactive Problem-Solving: Demonstrated rapid learning, proactive initiative-taking, and efficient debugging in adapting to new challenges.
C++ Framework Pioneer for polar code decoders, featuring meticulously designed bit-exact versions with quantization for streamlined hardware development and testing.
Advanced Hardware Architect for various polar decoder architectures, consistently achieving remarkable performance metrics in throughput, latency, area/energy efficiency, and error correction capabilities.
Educational Contribution in shaping and delivering coursework, notably contributing to subjects like Computer Organization, Digital System Design, and Digital Logic, enriching the educational experience for students.
ASIC Development & Tapeout: Led the complete lifecycle of ASIC development, overseeing the chip tapeout process for advanced arithmetic design units. Achieved successful implementation and optimization, contributing to cutting-edge hardware solutions.
Coursework Design Lead: Spearheaded the design and execution of coursework in Digital Logic, Electronics, Computer Architecture, and VLSI Design. Ensured engaging and comprehensive learning experiences for students across diverse subjects.
Energy-Aware Policies: Developed and implemented energy-efficient policies on Nehalem architecture, optimizing for CPUs and RAMs.
Intel Architecture Analysis: Analyzed cutting-edge Intel server and PC architectures using the SPEC CPU benchmark.
1st Rank in Department of Electrical Engineering with Dean's Honor List.
Specialization on: Computer Architecture, Digital Systems, ASIC Design.